Gallium Nitride (GaN) monolithic microwave integrated circuit (MMIC) biasing requires each individual MMIC to be biased independently at its own distinct gate bias voltage. This individual biasing of each die increases the cost of assembly, testing, and use. GaN gate bias voltage may vary across a range of bias voltages that is larger and more sensitive than traditional biasing techniques resolve. GaN devices belong to a family of semiconductors known as wide-band semiconductors. Wide band gap semiconductors refer to materials with band gaps significantly greater than those of commonly used materials such as silicon (Si) or gallium arsenide (GaAs), by way of example.
Biasing a field effect transistor (FET) of a MMIC requires applying a voltage level (e.g. bias voltage) to the gate of the FET, which causes a desired current to flow between the source and drain of the FET during a quiescent state of the FET. Due to differences within semiconductor wafers and fabrications processes, each FET fabricated from a given semiconductor wafer requires its own particular (unique) bias voltage. The bias voltage required for a particular FET is determined by production testing at the foundry. The tested FETs are binned according to their identified bias voltage levels. When the FET is installed in a circuit, the circuit must be designed to account for the FET's required bias voltage to ensure proper operation.
One traditional approach for biasing a FET is the use of a voltage divider or “ladder”. This approach utilizes resistors connected in series, with the gate of the FET to be biased connected between first and second resistors of the series-connected resistors (i.e. “ladder”). The series-connected resistor ladder is placed between a positive voltage source and ground. Bond pads are provided between adjacent resistors of the resistor ladder. A negative voltage source may be connected to a selected bond pad causing a voltage drop across each resistor between the selected bond pad and the positive voltage source. This creates a voltage level at the point between the first and second resistor at the point where the gate of the FET is connected to the resistor ladder. By selectively connecting the negative voltage source to one of the bond pads, a voltage level at the gate of the FET is produced in discrete steps based on the bond pad selected. In some applications, the discrete steps are in increments of about 0.2 volts. For FET applications using semiconductors such as silicon-based semiconductors or gallium arsenide (GaAs), the range of bias voltage levels is relatively small. This makes the discrete voltage steps of 0.2 volts achievable by a resistor ladder practical for providing bias voltages to these devices. However, when using semiconductors such as GaN, the difference in bias voltages required for FETs from a single semiconductor wafer may span several volts. Thus, a resistor ladder providing voltage steps of only fractions of a volt would require too many resistors and contact points to be practicable. During testing, because of the wide range of possible bias voltages required to accommodate the variance in GaN-based dies, many of the fabricated devices cannot achieve the necessary bias voltage and fail production testing. These failed components are discarded. Accordingly, high failure rates have a detrimental effect on yield and overall costs.
Biasing GaN MMICs adds complexity to the assembly, testing and implementation of designs using these types of semiconductor devices. As stated above, each MMIC must be biased according to its own specific gate voltage. Traditional self-biasing techniques, such as resistor ladders, cannot be used in GaN devices because of the wide range of bias voltage levels needed across GaN devices. Using the voltage ladder described above, each MMIC is typically wired to a voltage tap determined during production testing to provide the approximate required bias voltage. GaN devices require more taps than is generally feasible. To accommodate the number of taps and resistors needed, additional design and customization of assemblies is frequently required. These approaches are expensive and require a significant amount of additional labor. Adding to these disadvantages, as the MMIC bias level shifts toward the edge of a voltage bin, performance of the MMIC degrades.
Savings can be achieved by reducing the area currently required for extensive bias ladder systems. Smaller, less costly chips should result in less expensive aggregated modules. This becomes even more important as system operating frequencies increase and arrays dictate smaller and smaller RF modules.
FIG. 1 shows a conventional biasing technique using a source resistor 101 coupled to the output transistor 105. Field effect transistors (FETs) require a gate voltage more negative than the source voltage. Bias circuit 100 achieves a gate-source bias by providing a source resistor 101 connected to the source 103 of FET 105. Current through source resistor 101 generates a source voltage that is greater than the voltage at the gate 107. Grounding the gate 107 via inductor 109 forces the gate bias voltage below the source voltage. The desired gate-source voltage differential will determine the resistance value of source resistor 101. For GaN transistors, gate-source voltages as high as three volts may be required, which in turn, require a large source resistor. However, large source resistance results in lower amplifier gain and power output. Gain may be determined by the ratio of the drain to source resistance values (Rd/Rs). Thus, a large Rs will lower gain. Furthermore, a large source capacitor 111 can result in FET oscillation. Rs can be minimized by use of a source capacitor 111 connected in parallel to the source resistor 101. However, the large source resistance required by GaN transistors forces the use of a large source capacitor 111. Large source capacitor 111 applies large amounts of negative source resistance, which causes FET 100 to oscillate as the voltage at source 103 varies with respect to the voltage at gate 107.
Also the current handling capacity of resistor 101 will limit the size of GaN transistor 103. For example, in an integrated circuit such as a MMIC the current handling capability of resistor 101 is limited to 0.9 mA/um. The maximum resistor width is generally 100 um so the GaN transistor is limited to 90 mA. This is too small to be useful in a power amplifier application. A second example in a discrete assembly a large resistor 101, can handle currents as high as 1 amp, but such a resistor 101 will be so large that the maximum frequency will be practically limited to less than one GHz.
FIG. 2 shows a conventional bias circuit 200 which includes temperature compensation. A reference FET 201 is connected to a positive voltage source 211 at its drain by a pair of series connected Schottky diodes 209. The reference FET 201 is connected to a negative voltage source 205 at its gate 203. The source of the FET 201 is connected to the negative voltage source 205 via a pair of series connected Schottky diodes 207 for producing a source voltage that is greater than the gate voltage. A voltage drop created by current flowing through Schottky diodes 209 produces a bias voltage level 213, which is applied to the gate of a radio frequency (RF) FET. Bias circuit 200 does not allow for different drain currents. Additionally, bias circuit 200 does not provide a level shift, which is necessary to drive common source devices. Moreover, the use of Schottky diodes 207, 209 increases processing costs. Also the current handling capacity of diodes 207 and 209 will limit the size of GaN transistor 303. For example, in an integrated circuit such as a MMIC the current handling capability of diodes 207 and 209 is limited to 0.1 mA/um. The maximum diode width is generally 100 um so the GaN transistor is limited to 10 mA. This is too small to be useful in any amplifier application.
Alternative systems and methods for self-biasing of a GaN transistor are desired.